Document Outline

• Declaration of Authorship
• Abstract
• Abstract greek
• List of Figures
• List of Tables
• Abbreviations
• 1 Introduction
  • 1.1 Embedded Systems
  • 1.2 Intellectual Property Cores
  • 1.3 Soft Microprocessors
    • 1.3.1 The Picoblaze Soft Microprocessor
    • 1.3.2 The Microblaze Soft Microprocessor
    • 1.3.3 The Xtensa Microprocessors
    • 1.3.4 LEON Microprocessor
    • 1.3.5 The OpenRISC Microprocessor
  • 1.4 Floating point arithmetic
    • 1.4.1 Trade offs between range and precision
    • 1.4.2 The floating point representation
    • 1.4.3 The IEEE 754 standard
    • 1.4.4 Basic IEEE 754 formats
  • 1.5 The IEEE 754 double precision floating point format
    • 1.5.1 The sign bit
    • 1.5.2 The exponent
    • 1.5.3 The significand
    • 1.5.4 Floating point normalization
  • 1.6 The goals of the thesis
  • 1.7 The Following work structure
• 2 The processor
  • 2.1 Architecture Highlights
    • 2.1.1 Datapath Size
    • 2.1.2 Subword Parallelism
    • 2.1.3 Predication
  • 2.2 Processor Implementation
  • 2.3 The first pipeline stage
    • 2.3.1 The Program Counter
    • 2.3.2 Program Counter Metric Statistics
    • 2.3.3 The Instruction Memory
    • 2.3.4 The data multiplexers
    • 2.3.5 The stage 1 data flow
  • 2.4 The second pipeline stage
  • 2.5 The third pipeline stage
    • 2.5.1 The Arithmetic Logic Unit(ALU)
    • 2.5.2 The Multiplier
    • 2.5.3 The Mix Unit
    • 2.5.4 The Shifter Unit
    • 2.5.5 Predicate File, Sign Extension Unit and multiplexers
  • 2.6 The fourth Pipeline
  • 2.7 The Fifth Pipeline Stage
    • 2.7.1 The register Input Unit
  • 2.8 The control Unit
    • 2.8.1 The operation decoder
    • 2.8.2 The stall unit
    • 2.8.3 The Flag Unit
  • 2.9 The processor top module
  • 2.10 Hazards and data corruption
    • 2.10.1 Read after write hazard
    • 2.10.2 Branch Hazards
    • 2.10.3 Structural Hazards
    • 2.10.4 Pipeline bubbling
    • 2.10.5 Register Forwading
• 3 The Floating Point Unit(FPU)
  • 3.1 Floating point addition-subtraction
    • 3.1.1 FPU Adder testbench
  • 3.2 Floating point multiplication
  • 3.3 Floating point division
  • 3.4 The FPU Top Module
• 4 The Processor Customization
  • 4.1 Compatibility
  • 4.2 ISA Customization
  • 4.3 Wiring and stalling
  • 4.4 Processor Testing
    • 4.4.1 Data Synchronization
    • 4.4.2 Execution Testing
• 5 Tools Utilized
  • 5.1 VHDL
    • 5.1.1 The IEEE standard
    • 5.1.2 Advantages
  • 5.2 FPGAs
    • 5.2.1 History
    • 5.2.2 Modern developments
  • 5.3 The Xilinx Virtex ML605
  • 5.4 Xilinx ISE
    • 5.4.1 The CORE Generator
  • 5.5 Modelsim Simulation Program
• 6 Conclusions
  • 6.1 Acknowledgements and Compromises
  • 6.2 Future Work
• A RTL schematics
• B PLX 1.1 Instruction Set Architecture
• C Segments of Code
• D Module control signals
• Bibliography