Chapter 2. The processor
21
M2 provides the address for the Rs1 register and the value is either in bits 17 down to
13 or in bits 22 down to 18. Both multiplexers are controled by the control unit and
their value is automatically provided.
2.3.5
The stage 1 data flow
Stage one operates in one clock cycle. The program counter operates on the falling
edge of the clock and provides the new value when clock has value ’0’. The instruction
memory operates on opposite clock cycle, i.e. rising edge of the clock. This allows
the instruction memory to provide the new instruction in the same clock cycle as the
program counter produces the new value, merging the two components in one stage. As
soon as the clock takes the low value the program counter provides a new 64bit value.
However only the 9 least significand bits are used to acquire the new instruction memory
since its size is 512 words, hence 9 bits are required to encode all the addresses. The
program counter produces a 64 bit value because the value needs to be used in the next
stages. As soon as the instruction memory receives a new value it provides the new
instruction which is driven in the control unit. The value that is fed in the control unit
is the concatenation of the following bit strings: a) 28 down to 23, b) 17 down to 16, c)
7 down to 0. Bits 22 down to 0 and 31 down to 29 are driven to the multiplexers M1
and M2. The control unit provides the proper signals for this stage immediately after
the new value is provided by the instruction memory.
2.4
The second pipeline stage
The second stage contains the reading part of the register file and the two data mul-
tiplexers. The register file stores 32 64bit words. Table
displays all the ports for
the register file. The reading of the data in the register file is done in the falling edge
of the clock while the writing, which is done in stage 5, is done in the rising edge so
as to avoid data corruption in case a read an write instruction of the same register is
performed simultaneously. This stage also contains the two bypassing multiplexers M3
and M4, more details about the data bypassing in the Hazard Dealing section.
Figure
displays a short simulation of the Register File. After the module is being reset
two values 1024 and 1025 are driven to the addresses 13 and 14 respectively. However