Chapter 2. The processor
33
Table 2.12: The Flag Unit ports
Name
Type
Size
Explanation
illegal
input signal
1
illegal signal
trap in
input signal
1
trap instruction
ALU OUF
input signal
8
ALU overflow/underflow
FPU OUF
input signal
2
FPU overflow/underflow
trap o
output signal
1
trap flag
ALU OU o
output signal
8
ALU overflow/underflow flag
FPU OU o
output signal
2
FPU overflow/underflow flag
illegal o
output signal
1
illegal flag
“test bit” produces a ‘1’. The ALU overflow/underflow flag is raised when an overflow
or underflow occurs in the ALU adder. This flag is 8 bits long one bit for every 1 byte
adder contained in the adder.
2.9
The processor top module
The maximum achieved frequency for the processor in the specific board is 58,289 MHz.
However calculating the instructions per second requires real time simulation with desig-
nated algorithms. The distribution of the frequency, at which every instruction is used,
is crucial to calculate properly the performance. The instructions that require more than
one clock cycle to complete are: Addf 3 cycles, Subf 3 cycles, Divf 55 cycles, Sqrrtf 59
cycles, Cmp 3 cycles, Cmpi 3 cycles, Jmp 2 cycles, Load 5 cycles , Loadi 5 cycles, Loadx
5 cycles, Paddincr 3 cycles, Psub 2 cycles, Psubdecr 3 cycles. According to Lee[
], cmp
appears on average of 4%, Jmp 1.5%, load 5%, loadi 1%. We can assume that the rest
of the instructions with multi-cycle completion time have a negligible effect on the final
performance. Assuming that Addf appears on average of 5%, Subf 4%, Multf 2%, Divf
1% and Sqrrtf 1% we can calculate the instructions per second (IPS), using Eq.
IP S = A
1
× F
1
+ A
2
× F
2
+ A
3
× F
3
+ . . . + A
n
× F
n
(2.2)
Where A
n
the appearance frequency and F
n
= F
max
/required clock cycles. With this
formula we calculated the instructions per second for our implementation to be 52955260
IPS.