Chapter 3. The FPU
44
Figure
displays the simulation results for the divider. A and B are the two 64bit
numbers to be divided. The following numbers were used:
A = 1101010100010101010101010101110101010101001010101010101001111111
B = 1100111101011011010111011011011011010111011011011011011101100111
and the following result was produced:
R = 0100010110110000000000000001000100000000000000000000000000000000
After breaking down the result to the actual components we get the following:
Sign
A
= 1
Sign
B
= 1
Sign
R
= 0
E
A
= 10101010001
E
B
= 10011110101
E
R
= 10001011011
S
A
= 0101010101010101110101010101001010101010101001111111
S
B
= 1011010111011011011011010111011011011011011101100111
S
R
= 0000000000000001000100000000000000000000000000000000
The sign result is 0 i.e. positive since minus by minus is plus. The exponent result
is the difference between the two exponents with the addition of E bias = 1023,E
R
=
E
A
− E
B
+ 1023. The significand result is 1.S
R
= 1.S
A
/1.S
B
. The simulation lasts for
5600ms or 56 cycles of 100ms each. One cycle is the reset process and the rest 55 cycles
is the calculation of the result.
3.4
The FPU Top Module
In order to easily access and make use of the floating point processing units(Adder/Subtracter,
Multiplier, Divisor), a top module was created to include them. The RTL schematic can
be found here
. The synthesized top module has a maximum frequency of 81.155MHz
which is limited by the slowest component, the adder. In this implementation it is not
possible for the modules to operate simultaneously, however it is considered a necessary