Chapter 4. The Processor Customization
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4.4
Processor Testing
As it is clear the addition of new components and the customization of various com-
ponents compromises the integrity and functionality of the processor. There are many
parameters that need to be tested to reassure a 100% proper functionality such us tim-
ing, data synchronization, instruction hazards, resetting capabilities, interrupt signals
and many more. A very robust debugging can be performed with an assembler a com-
piler and various simulating scripts, however due to limited time these tools could not
be developed. A basic timing and data synchronizing as well as distinct instruction
execution were tested.
4.4.1
Data Synchronization
A problem encountered in the development of this processor and the pipeline design
was the data synchronization through the pipeline propagation. The problem arises
when data from different components and different time constraints are propagated to
the next pipeline stage. Since the processor is pipelined many stages contain modules
which operate with as well as without a clock signal. This is a problem since the module
operating on a clock signal can cause data to propagate at different cycles than modules
that don’t operate with a clock. The Register File reading stage is such an example. As
seen in Figure
, there are 3 main databuses propagating: Data from register R1, data
from the Register File and data from register R2. The pipeline registers for the Register
File address reading have been removed as they caused data to be desynchronized, since
they would require 2 clock cycles to propagate to the third stage.
In order to better visualize and verify the proper data propagation, a mirror design of
the processor’s RTL which simulates the data propagation through registers was created
as seen in figure
. Even though the second path involving all the major contains
two more clock dependent units, data arrives at the same clock cycle at the fifth stage
as seen in figure
. This is possible due to the fact that various components operate
at different clock cycles. The same behavior is expected from the processor since the
registers and combined with the sequential circuits form a similar mirror design. The
code for the sample mirror RTL design can be found in Appendix C