Chapter 2
The processor
In this chapter the whole process of designing and implementing the processor that was
used is explained in detail. Most of the soft processors available, are general purpose with
a main focus in flexibility and an all around usability. However all of these processors are
well understood and developed and there is very little room for customization. Almost all
the popular softcores have a development environment that fully supports customization.
As a result the processor chosen to be implemented here is based on ISA PLX 1.1[
an instruction set developed by professor Ruby B. Lee from Princeton University. It
is a small processor that supports parallel subword instructions and is intended for
multimedia processing. The full instruction set encoding tables can be found here [
Where needed the assumed register order in the instruction encoding tables is as follows:
1) Register Rd, 2) Register Rs1, 3) Register Rs3.
2.1
Architecture Highlights
The instruction set is designed for RISC architecture implementation. It is optimized for
high speed multimedia processing. There are two features that distinguish multimedia
processors from simple general purpose processors: Large amounts of parallel subword
data processing and use of low precision data[
]. Both of these features are charac-
teristics of the PLX instruction set. The processor utilizes 32 general-integer registers
numbered R0 to R31. The register size is the same as the word width and an be 32, 64
or 128 bits long. Adjusting the size does not require any changes to the instruction set.
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