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Chapter 2. The processor

a r c h i t e c t u r e o p _ d c d r of o p _ d e c o d e r is

b e g i n
p r o c e s s ( op , s u b o p )
b e g i n

c a s e op (15 d o w n t o 10) is
w h e n " 0 0 0 0 0 0 " = > - - jmp

P C _ c o n t r o l _ s i g n a l s

<= " 1 0 " ;

A L U _ c o n t r o l _ s i g n a l s

<= "0 X X X X X X X X X X X X X X X X X X X ";

M U L T _ c o n t r o l _ s i g n a l s

<= "0 X X X X X X X ";

S H I F T _ c o n t r o l _ s i g n a l s

<= "0 X X X X X X X X ";

M I X _ c o n t r o l _ s i g n a l s

<= "0 X X X X X ";

F P U _ c o n t r o l _ s i g n a l s

<= "0 XXX ";

S I G N _ E X T _ c o n t r o l _ s i g n a l s

<= ’X ’;

D A T A _ M E M _ c o n t r o l _ s i g n a l s

<= " 0 0 0 0 0 0 0 0 " ;

R E G I S T E R _ F _ c o n t r o l _ s i g n a l s

<= " 0 0 " ;

P R E D I C A T E _ c o n t r o l _ s i g n a l s

<= " 0 0 0 " ;

R E G _ I N P U T _ c o n t r o l _ s i g n a l s

<= " 0 0 0 0 " ;

i l l e g a l

<= ’0 ’;

Figure 2.15: The ”jump” instruction decoding

• The predicate signals unit. Responsible for controlling the predicate ﬁle and

each signals.

• The stall unit. Responsible for the stall signals.

• The illegal ﬂags unit. This unit produces the system ﬂags that are sent to the

program to determine program ﬂaws such us overﬂows and underﬂows.

• The Multiplexers unit. This unit controls all the multiplexers of the processor.

2.8.1

The operation decoder

This unit is responsible for decoding the instruction arriving from the instruction mem-

ory and dispatching the appropriate signals. This module is purely composed of combi-

national logic and the input and output ports can be seen at table

2.9

. The decoder is

a vast array of decoders and multiplexers. It’s a very simple circuit in the design but a

very extensive one. A future addition could be to be automatically generated by another

software program. The way it operates is the following. For every unique combination

of the operation and sub-operation it receives it produces the respective unique output

signals. Figure one shows a sample code for the ”jump” instruction. The MSB of ev-

ery output signal is the ”enable” signal, ’1’ for enabled ’0’ for disabled. Since only the

program counter is involved in the ”jump” instructions all the modules are disabled but

the PC. The rest of the bits are the control signals of each module which can be seen in