Chapter 1. Introduction
13
explanation is given in chapter ******* about the Floating point implementation). If
the MSB is zero then the significand must be shifted left by one and a zero must be
concatenated to the right of the LSB as displayed in figure
left shift by one
←−−−−−−−−−−
64 bits
0.111010100...111
64 bits
1.111010100...110
a zero has been concatenated
←−−−−−−−−−−−−−−−−−−
(1.4)
1.6
The goals of the thesis
It is crucial at this point to mention the goal of the work implemented as well as the
motivation. This thesis work presents a way of designing and creating a soft processor
which is based on ISA PLX 1.1[
]. Furthermore it is also important to highlight the
flexibility of soft processors and for this reason, we implemented a customization on this
processor by adding a custom FPU core. The whole process is described in full detail in
the following chapters.
The full methodology of how to customize an IP-core and adjust it to someone’s needs
is presented, allowing someone by using it to create and customize his own cores. This is
very important since it can save up valuable time which would be otherwise spent in an
effort to figure out the most efficient way to accomplish the creation and customization
of a module.
A complete implementation of a Floating Point Arithmetic Unit is also presented, pro-
viding a clear picture as to how it was implemented and tested. An existing design,
specifically created to target FPGA devices, was used[
] and implemented. A test-
bench was also created allowing the user to verify the integrity of some features of the
FPU.