Chapter 3. The FPU
41
t y p e d e f u n s i g n e d l o n g l o n g int u n i t 6 4 ;
v o i d c o n v _ t o _ b i n ( u n i t 6 4 s , int * d , int n ) {
int i ;
u n i t 6 4 tmp = s ;
for ( i = n -1; i > -1; i - -) {
d [ i ]= tmp %2;
tmp / = 2 ;
}
}
u n i t 6 4 c o n v _ d e c ( int * p , int m , int n ) {
int i ;
u n i t 6 4 tmp =0;
for ( i = m ; i < n ; i ++) {
if ( p [ i ] = = 1 )
tmp += pow (2 , n -1 - i );
}
r e t u r n tmp ;
}
Figure 3.3: The two conversion functions
3.2
Floating point multiplication
The multiplying process is much simpler than the addition/subtraction. For two num-
bers A and B with A = ±S
A
∗ 2
E
A
and B = ±S
B
∗ 2
B
B
the first step is to calculate
the sum E
A
+ E
B
− E
bias
where E
bias
= 1023. The E
bias
is subtracted since the expo-
nents are in the form of E + 1023 and therefore the extra E bias must be subtracted.
The next step is to multiply the significands and normalize the result. Similarly to the
adder there are many implementations that can be used. The one used here is the one
described in [
] and the corresponding RTL schematic can be found in Appendix A
. However some alternations were implemented. The main alternation is that the
multiplier operates in 1 cycle instead of 10. This is done because the actual multiplying
unit implemented is not the one described in [
] and instead a classic IEEE std logic
1164 multiplier was used which occupies only 20% more area.
The multiplier is a combinational circuit so the maximum frequency is calculated by the
propagation delay, F
max
= 1/(8.535ns) = 117M Hz. Table
shows the area utilization
for the specified board. The power consumption is 1.293Watts.
Figure
displays the simulation results for the multiplier. A and B are the two 64bit
numbers to be multiplied. The following numbers were used:
A = 1101010100010101010101010101110101010101001010101010101001111111
B = 1100111101011011010111011011011011010111011011011011011101100111