Chapter 4. The Processor Customization
50
Figure 4.1: Stage 2 of the pipeline
For addf the new encoding is ”101100”, for subf ”101101”, for multf ”101110” and divf
”101111”. Appendix C Figure
displays the signals encoded to run the instructions.
4.3
Wiring and stalling
The next necessary step is to connect and fully support the function of the new module.
The FPU was placed in the stage 3 of the pipeline, where all the other data processing
units are also placed. The adaptations there are in the form of a few simple extra
wiring and the new control signals targeting the FPU. The outputs from the two data
multiplexers M6 and M5 are now also driven to the respective RS1 and Rs2 inputs of the
FPU. Multiplexer M7 that is responsible of providing the proper result to the next stage
has the output of the FPU now also connected. Control signals are also connected to
the new module. Regarding the top module level no other alternation must take place.
The component that requires some alternations is the control unit.The control unit being
responsible for organizing synchronizing and controlling all the modules and units of the
processor needs to adapt. The first major change is the internal wiring of the control unit,
as it needs to support extra inputs, outputs, flag signals, and control signals. The first
change is the addition of three more outputs in the stage 3 control signals output, which
are the new FPU control signals. Next a signal for the overflow/underflow FPU output
and a new flag for the FPU overflow/underflow. Since all the FPU instructions are
multicycle a signal ”done” is also connected to inform the control unit that the operation
has been completed. This is done to avoid adding unnecessary counting circuits in the
control unit which would not be area efficient. The FPU instructions have also been
added to the stalling list where the processor stalls until the ”done” signal is activated.