Chapter 2. The processor
20
Table 2.2: The Instruction Memory Ports
Name
Type
Size
Explanation
clka
input signal
1
clock signal
wea
input signal
1
memory initialization signal
addra
input signal
32
memory address
dina
input signal
32
input data
douta
output signal
1
output data
Table 2.3: The program counter ports
Name
Type
Size
Explanation
Sin
input signal
2
functionality signals
Rd
input signal
64
Rd register value
Imm
input signal
23
immediate value
clk
input signal
1
clock signal
res
input signal
1
reset signal
stall
input signal
1
stall signal
PC
output signal
64
program counter output
2.3.3
The Instruction Memory
The instruction memory used is a 512x32bits block memory as mentioned earlier. The
memory is generated be the Xilinx CORE Generator System[
]. This tool provides an
easy way to communicate with the on-board memory found on the FPGA used. A more
thorough explanation for the tool is given in chapter 6. This module has 3 ports plus
two ”hidden”. The 3 standard ports are a 9bit address input port, a 32bit output data
port and a 1bit clock input port. The ”hidden” ports are the ones used to initialize the
memory, i.e. to store the program to be executed. There is a 1bit initialization signal
which stalls the memory and the processor and a 32bit signal carrying one instruction
per clock cycle. To initialize the memory one simply has to raise the initialization signal
to high, which automatically stalls the processor, and then input the instructions one
per clock cycle to subsequent addresses. The standard frequency for the memory module
is 144MHz. Table
displays all the port signals of the Instruction Memory.
2.3.4
The data multiplexers
Stage one of the pipeline contains two multiplexers that provide the two addresses re-
quired for the register file. Multiplexer M1 provides the address for the Rs2 or Rd
register depending on the instruction. There are three possible locations in the instruc-
tion word: a) bits 12 down to 8, b) bits 17 down to 13, c) bits 22 down to 18. Multiplexer