Appendix C
Segments of Code
The VHDL testbench
- - FPU . ADD / S U B _ t e s t b e n c h - -
- - A N G E L O S NTASIOS - -
l i b r a r y i e e e ;
use i e e e . s t d _ l o g i c _ 1 1 6 4 . all ;
use std . t e x t i o . all ;
e n t i t y a d d _ s u b _ t e s t b e n c h is
end ;
a r c h i t e c t u r e
a d d _ s u b _ t e s t b of a d d _ s u b _ t e s t b e n c h is
c o m p o n e n t A D D E R _ F is
p o r t (
A
: in s t d _ l o g i c _ v e c t o r (63 d o w n t o 0);
- - A
B
: in s t d _ l o g i c _ v e c t o r (63 d o w n t o 0);
- - B
OP
: in s t d _ l o g i c ;
- - OP 0=+ 1= -
R
: out s t d _ l o g i c _ v e c t o r (63 d o w n t o 0);
- - R
U_O
: out s t d _ l o g i c _ v e c t o r (1 d o w n t o 0);
- - u n d e r f l o w / o v e r f l o w
CLK
: in
s t d _ l o g i c ;
- - C l o c k
E N A B L E
: in
s t d _ l o g i c ;
- - E N A B L E
R E S E T
: in
s t d _ l o g i c ;
- - R E S E T ( G l o b a l )
d o n e
: out s t d _ l o g i c
);
end c o m p o n e n t ;
s i g n a l c l k _ g : s t d _ l o g i c := ’0 ’;
80