Chapter 1. Introduction
6
1.3.3
The Xtensa Microprocessors
Tensilica’s Xtensa technology provides a variety of soft processors for embedded systems.
This processor family is focused mainly in flexibility and customizability. A series of
options is offered from which to choose the ones that are needed. One important key
feature is that they are extensible in that custom instructions and custom units can be
added to the processor. This feature is supported by a custom Verilog language created
by Tensilica, the Tensilica Instruction Extension, which is used to describe the new
]. An automated HDL generator is also available for this processor, which
creates HDL modules of the customized processor.
1.3.4
LEON Microprocessor
LEON is a 32-bit CPU microprocessor core, based on the SPARC-V8 RISC architecture
and instruction set. It was originally designed by the European Space Research and
Technology Centre (ESTEC), part of the European Space Agency (ESA), and after that
by Gaisler Research. It is described in synthesizable VHDL. LEON has a dual license
model: An LGPL/GPL FLOSS license that can be used without licensing fee, or a
proprietary license that can be purchased for integration in a proprietary product. The
core is configurable through VHDL generics, and is used in system-on-a-chip (SOC)
designs both in research and commercial settings.
The LEON project was started by the European Space Agency (ESA) in late 1997 to
study and develop a high-performance processor to be used in European space projects.
The objectives for the project were to provide an open, portable and non-proprietary
processor design, capable to meet future requirements for performance, software com-
patibility and low system cost. Another objective was to be able to manufacture in a
Single event upset (SEU) sensitive semiconductor process. To maintain correct opera-
tion in the presence of SEUs, extensive error detection and error handling functions were
needed. The goals have been to detect and tolerate one error in any register without
software intervention, and to suppress effects from Single Event Transient (SET) errors
in combinational logic.
The LEON family includes the first LEON1 VHSIC Hardware Description Language
(VHDL) design that was used in the LEONExpress test chip developed in 0.25 μm