Chapter 4. The Processor Customization
49
be easily adjusted to a different word size. Other module such as shifters or adders
are more easy to make use off, usually by adding two or as many as required parallel
modules working together.
A future work addition, supports the ability to use multiple FPUs and other modules
for testing purposes. This is achieved by creating a general interface of ports which all
the same class modules must comply to. Those that have a different interface can be
adapted so they can be used in those designs. A series of other steps and alternations
must take place in order to support this implementation, which are clearly presented
4.2
ISA Customization
The first adaptation that needs to be done is to the instruction set.
The required
instructions to support the floating point calculations do not exist. For this purpose
4 simple 32bit instructions were created each for the perspective calculation. These
instructions are just the basic ones that are required for the FPU to function, however
more complex instructions can be added that involve for example immediate values and
shifted results.
The four new instructions added are the following:
1. addf This is the instruction for the floating point addition between two numbers.
2. subf This is the instruction for the floating point subtraction between two num-
bers.
3. divf This is the instruction for the floating point division between two numbers.
4. multf This is the instruction for the floating point multiplication between two
numbers.
No further encoding slots or bits had to be added since several encoding slots were free,
figure
displays the encoding of the addf instruction. Four consecutive slots were
occupied in order to easily handle them. These encoding slots would previsouly raise an
”illegal operation” flag, however they can now be used for the floating point instructions.