Abstract
The ever growing need for flexibility and low production cost in hardware implemen-
tations, has led to a wider use of reprogrammable and reconfigurable hardware such
as PLDs and FPGAs, which can be programmed with hardware description languages.
Using reconfigurable hardware provides the option to customize existing soft-cores and
soft processors in order to adapt to different design requirements.
In this thesis, an implementation of a processor based on the PLX 1.1 instruction set is
presented. Since the processor is intended for multimedia data processing, it is necessary
to include a floating point arithmetic unit. All the required steps that had to be taken in
order to embed a floating point unit in the processor are described in detail. The whole
design and implementation process of the soft core microprocessor as well as the FPU
are presented, along with the customization by embedding the double precision FPU. All
the stages of the work are accompanied by simulation results and FPGA implementation
metrics.