Chapter 2. The processor
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2.7
The Fifth Pipeline Stage
Stage five is the write back stage where the register file is updated. It is critical to point
out that if the predicate bit of the instruction is zero at this point no update will take
place. The register file write back operates in the rising edge of the clock to avoid data
corruption in case the same register is read and written in the same clock cycle.
2.7.1
The register Input Unit
This unit is used to execute the instructions ”extract”, ”deposit” and ”loadi” which
require, besides the standard Rs1 or Rs2 registers, also the Rd register to be processed.
As a result the Rd register needs to be read and written in the same instruction. This is
achieved by having the Rs1 processed normally and the Rd read and propagated through
the pipeline to the register input unit. Here all the necessary replacements take place
according to the instruction executed. The other option would be to make the register
file in such way to have the ability to update specific bits and bytes from various words
which would make it even more time consuming and area inefficient.
2.8
The control Unit
The control unit is responsible for monitoring the proper function of the processor and
sending the proper signals to all the stages. The control unit implemented is a hard-
wired control unit. This means that generally it uses sequential logic units, featuring a
finite number of gates that can generate specific results based on the instructions that
were used to invoke those responses. Hardwired control units are generally faster than
microprogrammed designs. The hardwire feature of the control unit renders it fast but
inflexible. However its easier to implement in a reprogrammable environment such as
the FPGA and much faster. Figure
Appendix A, displays the RTL schematic of the
control unit. Table
displays all the ports used by the control unit.
The control unit contains 6 components:
• The operation decoder. Responsible for decoding the instructions.
• The Bypass Unit. Responsible for data bypassing and forwarding.