Chapter 1. Tools Utilized
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their designs, perform timing analysis, examine RTL diagrams, simulate a design’s reac-
tion to different stimuli, and configure the target device with the programmer. Through-
out the designing, making and testing the processor this tool was used extensively since
the target was to create a design that was intended to be implemented in hardware.
Many HDL designs that appear functional and simulate properly in simulating pro-
grams and designs are in fact not feasible to implement in hardware. Another feature
helpful to the process is the fact that ISE can detect various bugs which would not be
otherwise detected easily, e.g. unconnected wires, bad connections between modules, FF
latches and unused signals.
The edition that was used is the Web edition, which is a free version of Xilinx ISE
that can be downloaded at no charge. It provides synthesis and programming for a
limited number of Xilinx devices. In particular, devices with a large number of I/O pins
and large gate matrices are disabled. The low-cost Spartan family of FPGAs is fully
supported by this edition, as well as the family of CPLDs, meaning small developers
and educational institutions have no overheads from the cost of development software.
All the speed, power and area estimations were generated by this program.
5.4.1
The CORE Generator
In order to utilize the on board memory which is embedded on the FPGA board, a series
of time consuming and difficult synchronization constraints and interface problems had
to be dealt with. A series of approximately 100 pins and signals have to be set appro-
priately for the memory interface. Xilinx offers a few tools to utilize and communicate
with the on board memory through the CORE Generator. The CORE Generator offers
the choice to create custom Xilinx IP Cores to utilize in the project. Some of these IP
Cores are used for memory interface. For our purposes the Block memory generator was
used which created a block-like interface memory Figure
In the processor design two separate memories are used, the instruction memory and the
data memory. The instruction memory is 512x32bits and the data memory 1024x64bits.
After following a few steps in a generating wizard the memory is created with the
interface shown in figure
and the VHDL code in figure