Chapter 1. Tools Utilized
65
Figure 5.4: Block memory generator
Figure 5.5: The instruction memory
c o m p o n e n t
i n s t r u c t i o n _ m e m o r y
p o r t (
c l k a
: in s t d _ l o g i c ;
wea
: in s t d _ l o g i c _ v e c t o r (0 d o w n t o 0);
a d d r a : in s t d _ l o g i c _ v e c t o r (8 d o w n t o 0);
d i n a
: in s t d _ l o g i c _ v e c t o r (31 d o w n t o 0);
d o u t a : out s t d _ l o g i c _ v e c t o r (31 d o w n t o 0)
);
end c o m p o n e n t ;
Figure 5.6: The instruction memory VHDL interface