Chapter 1. Tools Utilized
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simulations uninitialized values are easily detectable and thus easily corrected if neces-
sary.
VHDL has file input and output capabilities, and can be used as a general-purpose
language for text processing, but files are more commonly used by a simulation testbench
for stimulus or verification data.
5.1.2
Advantages
The key advantage of VHDL, when used for systems design, is that it allows the behavior
of the required system to be described (modeled) and verified (simulated) before synthe-
sis tools translate the design into real hardware (gates and wires). Another advantage
is that it allows the description of concurrent systems, where data flow is concurrent
and parallel, in contrast to conventional programming languages. Probably the largest
advantage is that the projects and modules created are reusable. For example once a reg-
ister file or an adder is created, it can be used again in other design with no alternations
as long as the interface is the same.
5.2
FPGAs
Field Programmable Gate Arrays are a family of hardware used for implementing re-
programmable hardware. FPGA configuration is generally specified using a hardware
description language (HDL), similar to that used for an application-specific integrated
circuit (ASIC). FPGAs by themselves do not actually implement any specific hardware
and they have no particular function. They contain programmable logic components
called ”logic blocks”, and a hierarchy of reconfigurable interconnects that allow the
blocks to be ”wired together”. FIgure
displays the general pattern of the cells in a
FPGA. Logic blocks can be configured to perform complex combinational functions, or
merely simple logic gates like AND and XOR. Figure
displays a simplified design of
the basic block of a Xilinx xc4000 FPGA. In most FPGAs, the logic blocks also include
memory elements, which may be simple flip-flops or more complete blocks of memory.
Logic resources are resources on the FPGA that can perform logic functions. Logic
resources are grouped in slices to create configurable logic blocks. A slice contains a