Chapter 6
Conclusions
In this thesis a thorough and detailed report and explanation of the process of designing,
implementing and customizing a processor was presented. The main purpose of this
work, was to show a simple procedure that can be followed in order to exploit the
flexibility offered by technologies such as the FPGAs and the HDLs, in order to adapt
hardware implementations to one’s needs. Many problems and possible bugs that could
arise, have been pointed out and a competent solution was presented alongside. This
work does not aim in the optimization of the core presented, but aims in presenting
generally the procedures followed to modify such modules.
6.1
Acknowledgements and Compromises
The size of the soft core created, somewhat compromises its integrity. Almost certainly
the processor is not bug-free, however a more than adequate implementation was pre-
sented. Since the design was created from scratch, there is no compiler or a machine
code generator available, which would help the debugging process. It is crucial at this
stage to point out that the design used to create the processor is not the optimum,
regarding speed, area and power consumption, nor was it designed to be such. The
process of optimizing requires work from many people and various fields of expertise.
The guideline for the design chosen was the basic MIPS pipelined processor and was
based upon this. All the optimization that occurred is in the pipeline design itself and
the module placement within it.
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