Chapter 3. The FPU
39
implemented(Appendix A
] where the whole dataflow is explained
in full detail.
The adder requires 3 clock cycles to complete the operation and the maximum achieved
frequency is 81.155MHz with a power consumption of 1.293Watts. Table
displays
the FPGA area utilization.
3.1.1
FPU Adder testbench
All the components of the adder where tested and verified with Modelsim. However the
fact that the adder is very complex and the possible results and the amount of values that
need to be tested is vast, a testbench has been created for this purpose. A testbench
is a program that provides a n automated method of testing and verifying modules.
Testbenches are usually composed by two parts. 1) The software simulating program,
which is a program written in any desired language(in our case c) that simulates the
hardware function in software. Since the same operation is much simpler and easier to
execute in software it is more reliable and stable. For example, while the adder consists of
approximately 1000 code lines, the corresponding C program consists of approximately
300 code lines.
The first step is to create a large number of random generated vectors that will be used
as test inputs. Since the vectors we need to use as inputs are two 64bit numbers the
rand() function was used with a number cap 2 in order to produce a random binary
number. This means that this function will provide a random number < 2 i.e. 0 or 1.
Figure
displays the code. The vectors are then stored in two arrays which are then
printed in a .txt file. Since the program only creates two vectors each time, Sa and Sb,
a simple windows shell script (.bat) program was created to rerun the program several
times and produce a desired amount of vectors. The .bat program is shown in Figure
. Since the rand() function uses a timer as a seed for the random generation a 1
second interval is created between the generated vectors to avoid identical copies.
After the vector are generated the program continues execution and simulates the
dataflow of the hardware. The results produced are stored in a .txt file along with
two flags for overflow or underflow. The problem that was encountered, was that the
hardware executes binary calculations but the same could not be done in software. So