Chapter 2. The processor
23
Table 2.5: The ALU Ports
Name
Type
Size
Explanation
Rs1
input signal
64
Rs1 register data
Rs2
input signal
64
Rs2 register data
S
input signal
1
operation signals
clk
input signal
1
clock input
enable
input signal
1
enable signal
reset
input signal
1
reset signal
Rd
output signal
64
Result data
trap
output signal
1
trap flag
OVF
output signal
8
overflow/underflow flag
T F
output signal
1
true/false flag
displays the ports used by the ALU module.This unit is responsible for the results
from the following instructions: Addi, And, Andcm, Andi, Cmp, Cmpi, Not, Or, Ori,
Padd, Paddincr, Pavg, Pcmp, Pmax, Pmin, Psub, Psubavg, Psubdecr, Psubavg, Subi,
Testbit, Xor, Xori.
ALU operates in one, two or three cycles depending on the operation. All the logic
calculations(or,nor,xor,not,and) require one cycle. Addition is performed also in one
cycle with the exception of the addincr instruction, which adds two values and increments
the result by one, which is done in two cycles. Subtraction is performed in two clock
cycles, since the subtraction is performed with an adder the two’s compliment method
is used. The value to be subtracted is first converted to its two’s compliment negative
equivalent, this is done using the formula
where n the two’s compliment number and
b the original number. In the first cycle a ’1’ is subtracted from the numbers’ compliment
and in the second cycle the addition takes place. Similarly if the number needs to be
decremented by 1 the operation takes up one more clock cycle. The ALU operates at
218,627 MHz and occupies 1% of the FPGA slices.
n = ¯
b − 1
(2.1)
The actual adder of the ALU is an array of 8 1byte adders. Since the addition can be
performed on a varying word size the smallest possible word size adder must be used.
The basic 1byte full adder is a standard full adder with the exception of providing an
extra output the carry out of the 6th half adder. This carry out is required in order
to detect overflows in signed calculations. Each adder has the carry out connected to