rtl2schematic - Educational RTL to Schematic Visualizer

rtl2schematic EDU

◀ SOURCE EDITOR

Source Editor

TOP MODULE:

Schematic

drag to pan • scroll to zoom • double click to drill down

Analysis & Metrics

Press ▷ Generate to synthesize design.

Synthesize design to view timing paths.

FPGA FAMILY

Select an FPGA family and press Map Design to view exact primitive usage (LUTs, Flip-Flops, Carry chains, DSPs, Block RAM).

Pin the current synthesis result as a baseline, make modifications to your RTL code, and re-generate to compare resource deltas (LUTs, FFs, DSPs, cells, depth).

No warnings or errors reported.

Naming & Optimisation

Readable Names (clean synthesized net names) As-Written (disable logic reduction & keep unreferenced nodes) Normalize Entity Names to Lowercase (e.g. top module "FA8" → "ENTITY fa8") Preserve Port Name Case (e.g. keep port identifier as "Cin" rather than "cin")

Conditional IF Port Order (Aldec WHEN/ELSE parity):

Schematic Layout & Port Alignment

I/O Ports Aligned (flush inputs to the far left and outputs to the far right) Order Input Ports by Code Appearance (top-to-bottom sequence matching RTL source code) Order Output Ports by Code Appearance (top-to-bottom sequence matching RTL source code) Color Input & Output Ports (Green for input pads, Red/Coral for output pads)

Schematic Detail Level

High-Level (Inferred RTL adders, muxes, registers) Gate-Level (Elementary gate primitive decomposition)

Gate-Basis Switcher:

Technology mapping decomposes all combinational functions into this elementary gate set.

FPGA Target Technology

Generic RTL Xilinx 7-Series (Artix-7 / Spartan-7) Lattice iCE40 Lattice ECP5 Gowin GW1N Intel Cyclone IV Intel Cyclone V

Clock Period (Static Timing Analysis)

ns

Used to compute timing slack and maximum frequency ($F_{max}$) against the critical path.

Examination / Submission Endpoint

Webhook URL where student schematic submissions and source codes are recorded.