Abstract

In today’s technology world, where data management and protection are primary

concerns,

security

and

cryptographic

applications

are

becoming

increasingly

important.

Introducing and evolving new cryptographic standards, such as SHA-3

(Secure

Hash

Algorithm

3),

marks

a

new

era

in

cryptography.

This

standard

offers increased security and resilience to cyber-attacks, surpassing previous systems’

efficiency and reliability.

Moreover, integrating such cryptographic mechanisms in

embedded systems, especially in Field-Programmable Gate Arrays (FPGAs), opens new

avenues for developing safer and more efficient technological solutions.

With their unique ability to be programmed and reprogrammed in the field,

the

FPGAs provide an ideal platform for implementing and optimizing cryptographic

applications.

Their flexibility allows adaptation to specific needs and responses to

different cryptographic challenges.

SHA-3,

as one of the latest and most secure

standards, offers improved security compared to earlier standards such as SHA-2. Its

implementation in FPGA enables faster and more efficient data processing, offering a

reliable way to protect data confidentiality and integrity.

Adopting such technologies is critical in the modern era, as the need for faster data

management is growing rapidly in various sectors, from e-commerce to government

organizations.

Integrating innovative cryptographic solutions such as SHA-3 into

FPGAs improves the security of digital systems and increases their flexibility and

ability

to

adapt

to

evolving

security

requirements,

ensuring

data

protection

in

a

rapidly

changing

technological

environment.

The

challenge

in

the

high-tech

sector

is

achieving

an

ideal

combination

of

processing

speed,

energy

efficiency

and cost reduction at the integration surface, especially in implementing advanced

cryptographic functions such as SHA-3.

In

this

thesis,

the

central

objective

is

the

development

of

efficient

acceleration

techniques for optimizing throughput and/or efficiency in cryptographic applications

implemented on FPGAs, with a particular focus on the SHA-3 cryptographic algorithm.

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