Βιβλιογραϕία
157
[199]
Kazuki Nakamura, Koji Hori, and Shoichi Hirose.
Algebraic Fault Analysis of
SHA-256 Compression Function and Its Application.
Information, 12(10):433,
2021.
[200]
Gorjan Alagic, Daniel Apon, David Cooper, Quynh Dang, Thinh Dang, John
Kelsey,
Jacob
Lichtinger,
Carl
Miller,
Dustin
Moody,
Rene
Peralta,
et
al.
Status
report
on
the
third
round
of
the
NIST
post-quantum
cryptography
standardization process.
US Department of Commerce, NIST, 2022.
[201]
Young
Beom
Kim,
Taek-Young
Youn,
and
Seog
Chung
Seo.
Chaining
optimization
methodology:
a
new
sha-3
implementation
on
low-end
microcontrollers.
Sustainability, 13(8):4324, 2021.
[202]
An Braeken.
Highly efficient symmetric key based authentication and key
agreement protocol using Keccak.
Sensors, 20(8):2160, 2020.
[203]
Thibaut Vandervelden, Ruben De Smet, Kris Steenhaut, and An Braeken. SHA
3 and Keccak variants computation speeds on constrained devices.
Future
Generation Computer Systems, 128:28–35, 2022.
[204]
Julián
Caba,
María
Díaz,
Jesús
Barba,
Raúl
Guerra,
Soledad
Escolar,
and
Sebastián López.
Low-power hyperspectral anomaly detector implementation
in cost-optimized FPGA devices.
IEEE Journal of Selected Topics in Applied Earth
Observations and Remote Sensing, 15:2379–2393, 2022.
[205]
Argyrios Sideris, Theodora Sanida, and Minas Dasygenis.
High throughput
pipelined
implementation
of
the
SHA-3
cryptoprocessor.
In
2020 32nd
International Conference on Microelectronics (ICM), pages 1–4. IEEE, 2020.
[206]
F
Assad,
F
Elotmani,
M
Fettach,
and
A
Tragha.
An
optimal
hardware
implementation of the KECCAK hash function on virtex-5 FPGA.
In
2019
International Conference on Systems of Collaboration Big Data, Internet of Things
& Security (SysCoBIoTS), pages 1–5. IEEE, 2019.
[207]
Hachem
Bensalem,
Yves
Blaquière,
and
Yvon
Savaria.
An
efficient
OpenCL-Based implementation of a SHA-3 co-processor on an FPGA-centric
platform.
IEEE Transactions on Circuits and Systems II: Express Briefs, 2022.
[208]
Jubin Mitra and Tapan K Nayak.
An FPGA-based phase measurement system.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(1):133–142,
2017.