Βιβλιογραϕία
152
implementations
of
five
SHA-3
finalists
using
Xilinx
and
Altera
FPGAs.
Cryptology ePrint Archive, 2012.
[152]
Pietro Nannipieri,
Matteo Bertolucci,
Luca Baldanzi,
Luca Crocetti,
Stefano
Di Matteo, Francesco Falaschi, Luca Fanucci, and Sergio Saponara.
SHA2 and
SHA-3 accelerator design in a 7 nm technology within the European Processor
Initiative.
Microprocessors and Microsystems, 87:103444, 2021.
[153]
Hassen Mestiri and Imen Barraj. High-Speed Hardware Architecture Based on
Error Detection for KECCAK.
Micromachines, 14(6):1129, 2023.
[154]
Brian Baldwin, Andrew Byrne, Liang Lu, Mark Hamilton, Neil Hanley, Maire
O’Neill, and William P Marnane.
FPGA implementations of the round two
SHA-3 candidates. In
2010 International Conference on Field Programmable Logic
and Applications, pages 400–407. IEEE, 2010.
[155]
Kentaro
Katayama,
Hidetoshi
Matsumura,
Hiroaki
Kameyama,
Shinichi
Sazawa,
and
Yasuhiro
Watanabe.
An
FPGA-accelerated
high-throughput
data optimization system for high-speed transfer via wide area network.
In
2017 International Conference on Field Programmable Technology (ICFPT), pages
211–214. IEEE, 2017.
[156]
Information Technology Laboratory Computer Security Division.
Example
Values - Cryptographic Standards and Guidelines: CSRC, 2016.
URL
[157]
Harris
Michail,
Athanasios
Kakarountas,
Athanasios
Milidonis,
and
Costas
Goutis.
A top-down design methodology for ultrahigh-performance hashing
cores.
IEEE Transactions on Dependable and Secure computing, 6(4):255–268,
2008.
[158]
Xilinx
Inc.
Xilinx
Power
Estimator
v2018.2.
User
Guide.
https://docs.xilinx.com/v/u/2018.2-English/ug440-xilinx-power-estimator,
2018.
[159]
Argyrios
Sideris,
Theodora
Sanida,
and
Minas
Dasygenis.
Hardware
acceleration design of the SHA-3 for high throughput and low area on FPGA.
Journal of Cryptographic Engineering, pages 1–13, 2024.
[160]
Sergiy Gnatyuk, Vasyl Kinzeryavyy, Karina Kyrychenko, Khalicha Yubuzova,
Marek Aleksander, and Roman Odarchenko. Secure hash function constructing