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HDL Generator by Dr. Minas Dasygenis
Components:
[[], [[0, 11]], [[], [0, 10]], [[], [], [0, 10]], [[2], [2], [2], [2], [], [2]]]
ComponentsList:
{"11": "ha1bit", "10": "fa1bit"}
Interconnection:
[[], [[[], [[-1, -1, -1, 0, 0, 0, 0], [-1, -1, -1, 1, 0, 0, 0]]]], [[], [[], [[1, 0, 1, 1, 0, 0, 0], [-1, -1, -1, 0, 1, 1, 0], [-1, -1, -1, 1, 1, 1, 0]]]], [[], [], [[] , [[2, 1, 1, 1, 0, 0, 0], [-1, -1, -1, 0, 2, 2, 0], [-1, -1, -1, 1, 2, 2, 0]]]], [[[1, 0, 1, 0, 0, 0, 0, 0, 0, 0]], [[2, 1, 1, 0, 0, 0, 0, 0, 1, 1]], [[3, 2, 1, 0, 0, 0, 0, 0, 2, 2]], [[3, 2, 1, 1, 0, 0, 0, 0, 3, 3]], [], [[-1, -1, -1, 1, 5 , 5, 0, 0, 5, 5]]]]
Create VHDL, Dot file & Schematic
Create VHDL only
.