s3esk_startup Project Status (05/09/2012 - 22:03:46) | |||
Project File: | otithes.xise | Parser Errors: | No Errors |
Module Name: | s3esk_startup | Implementation State: | Programming File Generated |
Target Device: | xc3s700a-4fg484 |
|
No Errors |
Product Version: | ISE 13.3 |
|
148 Warnings (148 new) |
Design Goal: | Balanced |
|
All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
|
All Constraints Met |
Environment: | System Settings |
|
0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 108 | 11,776 | 1% | ||
Number of 4 input LUTs | 193 | 11,776 | 1% | ||
Number of occupied Slices | 116 | 5,888 | 1% | ||
Number of Slices containing only related logic | 116 | 116 | 100% | ||
Number of Slices containing unrelated logic | 0 | 116 | 0% | ||
Total Number of 4 input LUTs | 195 | 11,776 | 1% | ||
Number used as logic | 123 | ||||
Number used as a route-thru | 2 | ||||
Number used for Dual Port RAMs | 16 | ||||
Number used for 32x1 RAMs | 52 | ||||
Number used as Shift registers | 2 | ||||
Number of bonded IOBs | 30 | 372 | 8% | ||
Number of BUFGMUXs | 1 | 24 | 4% | ||
Number of RAMB16BWEs | 1 | 20 | 5% | ||
Average Fanout of Non-Clock Nets | 3.70 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Τετ 9. Μαϊ 22:02:58 2012 | 0 | 115 Warnings (115 new) | 2 Infos (2 new) | |
Translation Report | Current | Τετ 9. Μαϊ 22:03:03 2012 | 0 | 1 Warning (1 new) | 1 Info (0 new) | |
Map Report | Current | Τετ 9. Μαϊ 22:03:08 2012 | 0 | 16 Warnings (16 new) | 3 Infos (3 new) | |
Place and Route Report | Current | Τετ 9. Μαϊ 22:03:23 2012 | 0 | 0 | 0 | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Τετ 9. Μαϊ 22:03:26 2012 | 0 | 0 | 4 Infos (4 new) | |
Bitgen Report | Current | Τετ 9. Μαϊ 22:03:34 2012 | 0 | 16 Warnings (16 new) | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | Τετ 9. Μαϊ 22:03:34 2012 | |
WebTalk Log File | Current | Τετ 9. Μαϊ 22:03:45 2012 |